Banner DF-G1-PR-Q7 Instruções de Operação descarregar pdf (Página 156)

9 – Maintenance

DPN 402197 © TSS (International) Ltd Page 5 of 26

Opto-isolated digital inputs to the ADC are:

❐ Analogue and digital power-down APD/DPD (through U12) to control the ADC

mode of operation. The ADC Board uses these for its self-calibration during initial-

isation.

❐ The clock signal from the Processor Board (through U13).

❐ Pre-amp gain control (through U14) to set the absolute gain of the pre-amplifier

using U6 of the Coil Pre-amplifier Board (see drawing 401105).

9.1.2.2 Processor Board

See drawing 401103 in section 10.

The Processor Board consists of three sub-sections:

❐ The ADC Interface (drawing 401103-4)

❐ The Processor Core (drawing 401103-2)

❐ The communications interface (drawing 401103-3)

1. ADC Interface (see drawing 401103-4).

The ADC Interface takes the three serial data lines from the ADC Board and multi-

plexes them onto one processor bus.

The three serial data inputs ‘SD1’, ‘SD2’ and ‘SD3’ arrive at the ADC Interface

through pins 3, 7 and 11 respectively of PL5. ‘SD1’ contains the starboard lateral and

vertical channels, ‘SD2’ contains the port lateral and vertical channels and ‘SD3’ con-

tains both fore-aft channels. The gate-control and frame-sync signals for each chan-

nel arrive at pins 4/6, 8/10 and 12/14 of PL5.

The ADC Interface uses three separate and identical channels to process all three

serial data inputs simultaneously. For each channel, the serial data that originates

from one coil passes into serial-to-parallel buffers under the control of the frame-sync

and clock signals.

When these buffers are loaded fully with data, an interrupt signal causes the proces-

sor to read each parallel port U53–U55 in turn. The processor knows which of the two

coils in each channel is being read, by the state of the gate-control signal that is

included as bit number 18 of the parallel output.

Once the processor has read the output buffers, data from the other coil in each chan-

nel passes into the buffers to be read by the processor.

Since all three channels on the ADC Interface run from the same clock, they will

remain synchronised perfectly and will always maintain the correct timing relation-

ships.

1 2 ... 151 152 153 154 155 156 157 158 159 160 161 ... 252 253

Sem comentários

Banner DF-G1-PR-Q7 Instruções de Operação Página 156